`timescale 1ns/1ns	

module SM3_Test;
		
	reg clk, rst;				// clock and reset signal
	reg W, R;					// SM3 write or read register
 	reg [31:0] m_i;				// message input
  	
	wire finish;
	wire [1:0] status;				// state of process
	wire [31:0] result;
	
	// SM3 Top Module
	SM3_Top M0(.clk(clk), .rst(rst), .write(W), .read(R), .mes_in(m_i), .status(status), .finish(finish), .result_out(result));
	
	// time clock generation		
	always #5 
		clk = ~ clk;	
	
	// messeage input and control signal input
	initial
		begin
			clk = 'b0;		// clock initialization, rst = 'b1
			rst = 'b1;
			
			# 2
				rst = 'b0;
				W = 'b1;
				R = 'b0;
			
			@(negedge clk);
				rst = 'b1;

			@(negedge clk);
				m_i = 32'h61626380;     //write 0
				
			@(negedge clk);  
				m_i = 32'h0; 			//1
     
			@(negedge clk);  
				m_i = 32'h0; 			//2
    
			@(negedge clk);  
				m_i = 32'h0; 			//3
		
			@(negedge clk); 
				m_i = 32'h0; 	  		//4
    
			@(negedge clk);  
				m_i = 32'h0; 			//5
     
			@(negedge clk);  
				m_i = 32'h0; 			//6
    
			@(negedge clk);  
				m_i = 32'h0; 			//7

			@(negedge clk); 
				m_i = 32'h0;	   		//8
    
			@(negedge clk);  
				m_i = 32'h0; 			//9
     
			@(negedge clk);  
				m_i = 32'h0; 			//10
    
			@(negedge clk);  
				m_i = 32'h0; 			//11

			@(negedge clk); 
				m_i = 32'h0; 	  		//12
    
			@(negedge clk);  
				m_i = 32'h0; 			//13
     
			@(negedge clk);  
				m_i = 32'h0; 			//14
    
			@(negedge clk);  
				m_i = 32'h00000018; 	//15	
			
			@(posedge clk)
				W = 'b0;

			@(posedge finish)
				R = 'b1;
				
			@(posedge clk)
				;						// initialize for read						
	
			@(posedge clk)				
				;						// read 0
				
			@(posedge clk)
				;						// 1
				
			@(posedge clk)
				;						// 2
				
			@(posedge clk)
				;						// 3				

			@(posedge clk)
				;						// 4

			@(posedge clk)
				;						// 5

			@(posedge clk)
				;						// 6

			@(posedge clk)
				R = 'b0;						// 7				
				
			@(posedge clk)
				R = 'b0;
		end

endmodule
	
